James Lu’s Research:


General Research Interests:

·          Information technology: micro- nano-electronics for future chips using hyper-integration

·          Heterogeneous system integration technology: mixed signal systems for defense, security, energy, environment and medical devices

·          Nanotechnology: nano materials, structures, devices and applications

·          Biotechnology: bio-micro-systems for bio and medical devices

·          Energy technology: solar cell and fuel cell technology


Lu’s research interests are in the field of micro- nano-electronics technology from theory and design to materials, devices, processing, and system integration; particularly in wafer-level 3D hyper-integration technology and micro-nano-bio interfaces for future chips, novel electron devices, interconnect technology, micro-system integration technology for micro-electrical-mechanical systems (MEMS); with long-term research interests in photonics, nanotech, bio-MEMS, bio-engineering, bio-inspired materials/devices and information processing/computation, and combination (3D integration) of nano/bio with CMOS based technologies.


As one of the pioneers in the field of wafer-level 3D hyper-integration for future chips, Dr. Lu has been leading 3D processing integration technology research programs at Rensselaer, supported by Microelectronics Advanced Research Corporation (MARCO), the Defense Advanced Research Projects Agency (DARPA), New York State (NYSTAR), Semiconductor Research Corporation (SRC), NASA and industries, and in collaborations with university colleagues, R&D institutions and industry partners.  He and his colleagues have developed a 3D integration technology platform for future ICs with high performance and functionality and low cost, and for low-cost Micro/Nano/Electro-Opto/Bio heterogeneous system integrations. He has worked in a broad range of fields, such as GaAs devices, GaN high power devices, Si bipolar device, terahertz electronics, interconnects in Si IC, advanced packaging, and high Tc superconductors.


Click here (719KB) to see a presentation of “Wafer-Level 3D Hyper-Integration Technology Platformfor more details.  



Current Research Programs:

·        DARPA BAA 03-25 – 3D ELECTRONICS: "Wafer to Wafer Alignment and Planarization Constraints for Wafer-Level 3D ICs" (subcontract to IBM)

·        SRC Customization Research, “Evaluation of Wafer Bonding Impact on Strain in Active Silicon in Monolithic Wafer-Level 3D IC Stacks”

·        NYSTAR: “Wafer-Level Vertically-Integrated Technology Platforms for Heterogeneous Hyper-Integration”, Focus Center-New York.

·        DARPA and MARCO: Interconnect Focus Center for Hyperintegration (Carbon-Nanotube Interconnects, 3D Power Delivery, Wireless Mixed Signal).

·        NYSTAR & Applied Nanoworks, Inc. “Characterization of the Nano-Oxide Particles Produced using Energy Efficient Manufacturing Processe"

·        International SEMATECH: “3D Interconnects”.

·        NYSTAR & Starfire Systems, Inc. “Exploration of Polymeric CVD precursors for the Synthesis of a Variety of Compounds for Optoelectronic and Energy Applications”.

·        NYSTAR & Superpower, Inc. “Development of Selective Chemical Etchants Suitable for Striation of Silver & YBCO Films on Superconducting Tapes for Power Delivery”.



Focus Center, New York: Rensselaer - Task Ic


Wafer-Level Three-Dimensional (3D) Hyper-Integration:

Technology Platforms and Design

for Heterogeneous, High-Performance Applications


Major Task – Task-I:

Electrical Interconnects



Hyper-Integration Technologies: Processing and Design


Goal: Establish technology platforms of, design circuits and architectures enabled by, and perform modeling and simulations on wafer-level three-dimensional (3D) hyper-integration for future chips with high performance, high interconnectivity, high functionality, and simplified processing with low cost, and for heterogeneous system integrations with mixed signal, wireless, THz, optical devices as well as nano devices and bio-chips/MEMS.


3D Hyper-Integration at Wafer-Level


Text Box:  
3D Hyper-Integration at Wafer-Level: Device wafers are aligned and bonded, then thinned and interconnected before additional stacking process or dicing to 3D chips.
            Wafer-level three-dimensional (3D) hyper-integration is one of the emerging chip architectures/technologies for future chips with high performance, high interconnectivity, high functionality, and simplified processing with low cost, and for heterogeneous system integrations. The Rensselaer 3D hyper-integration platform starts with fabrication of functional components (e.g., logic and memory) on separate wafers, followed by wafer aligning, bonding, thinning and vertical inter-wafer interconnection to integrate these functional components in a 3D stack.  3D integration offers significantly increased interconnect performance relative to 2D chips by reducing global interconnect delays, and is a promising approach to significantly increase functionality by heterogeneous integration of materials, devices, and signals. 3D integration has been aggressively pursued recently in the research community, with initial focus on microprocessors, application specific ICs (ASICs), and memories; and is extended to integration of RF, analog, optical, and micro-electro-mechanical systems (MEMS) onto silicon platforms. 

Key Challenges: 

-     Compatibility of 3D processes to present and future semiconductor processing and design protocols;

-     Wafer-level precision alignment, robust wafer bonding, damage-free wafer thinning and high-density inter-wafer interconnectivity;

-     Thermal-mechanical stress and thermal dissipation issues and constraints;

-     3D circuit design and performance evaluations.



3D Hyper-Integration Technology Platforms

            Rensselaer’s three main technology platforms include:

-  Via-last platform with wafer bonding with dielectric adhesive and copper damascene inter-wafer Interconnect;

-  Via-first platform with bonding of damascene-patterned metal/adhesive redistribution layers;

-  Optical inter-wafer interconnect platform with beam via and vertical cavity.



Current Research

            Current research focuses on three main areas, each with three separate subtasks:

               3D technology platform processes
-   wafer alignment and bonding
-   via-first wafer bonding of damascene-patterned metal/adhesive redistribution layers
-   low-temperature titanium-based bonding
               Novel technology applications and thermomechanical stresses
-   exploratory 3D integration technologies (nano-rod wafer bonding, metal contact to carbon-nano-tube, spintronics)  
-   optical coupling using 3D interconnect multilayers 
-   thermomechanical stress modeling and 3D design rules 
               3D-based design
-   memory-intensive processors in 2D compared to 3D 
-   next-generation transceivers for wireless communications 
-   monolithic DC-DC converter for processor 3D integration 


Major Accomplishments:

              3D technology platform processes

-    Via-chains for via-last 3D platform demonstrated and process issues delineated, with one-micron wafer-level alignment, thermal-mechanical-electrical robust wafer bonding and thinning, and copper-damascene patterned inter-wafer interconnects; robust bonding and thinning established in collaborations with SEMATECH and Freescale

-    Feasibility of via-first 3D platform demonstrated that offers the bonding strength of dielectric adhesive bonding (partially cured BCB) with the process integration advantages of via-first bonding;

-    Low-temperature Ti-based bonding to both silicon and oxide demonstrated, attractive for various 3D applications and needs.

              Novel applications and thermomechanical stress

-    Various innovative technologies explored for 3D interconnectivity, with 3D integration of metal nanorods, carbon nanotubes and micro-nano interface particularly attractive;

-    Optical beam vias with very high optical coupling with multilayer dimensions useful in forming optical 3D structures;

-    Thermomechanical stress modeling, indicating that micron-sized vias with small pitch and thin bonding adhesive can significantly reduce stress levels that can cause TCE-mismatch induced stress failure in Cu vias and in Ta liners.

              3D-enabled designs

-    The memory performance predictor (PRACTICS) developed for predicting the reduction of memory access time and SRAM dynamic power dissipation, allowing a more extensive comparison of 2D and 3D designs;

-    Design of next-generation transceivers enabled by technology partitioning possible with 3D implementation; promising for software radios with SiGe BiCMOS ADCs;

-    Buck-topology, monolithic DC-DC converter designs using advanced foundry design rules, indicating the promise of the buck converter, particularly as a point-of-load converter with low conversion ratio; the performance advantage of high capacitance density capacitors and magnetic film inductors shown by extensive circuit simulations.


External Collaborations:  University at Albany, MIT, IBM, Freescale Semiconductor, International SEMATECH, JPL, EVGroup, Motorola.

Text Box:  
FIB Image of bonded Freescale’s 130nm CMOS SOI Cu/Low-k Wafer









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